What is a delta delay in VHDL

8. Timing in VHDL

8.1 Simulation process

Strictly speaking, the concurrent instructions in VHDL are not processed in parallel. However, the concurrency is "simulated" by means of a special simulation sequence. In addition to the relationships between concurrent and sequential instructions, the differences between signal and variable assignments must also be taken into account.

At the architecture level, all instructions are "concurrent". Processes are also considered concurrent instructions. Sequential instructions are only available within processes, functions or procedures.

During the simulation, the times from the event list are processed one after the other. A simulation point in time generally consists of several so-called "delta cycles" which are offset by an infinitesimally small time, referred to as "delta". Each of these cycles consists of two successive phases:

1. Process execution phase ("process evaluation"):

The active processes up to the instruction or the next instruction are processed here. This includes the execution of all contained instructions except for the signal assignments, in particular the assignment of variables.

2. Signal assignment phase ("signal update"):

After the active process or processes have been carried out, the signal changes assigned there are carried out. This enables further processes or concurrent signal assignments to be activated. In this case, the cycle is run through again a "delta" later.

This process is repeated at a point in time until a stable state is established, i.e. until there are no more new signal assignments and no further process is activated.


Processes that use mixed variable and signal assignments and that show mutual dependencies between variables and signals therefore require special attention. With process communication, too, it must be ensured that the triggering signals change at the correct point in time.

The same as for the processes also applies to the assignment of signals by inconsistent instructions. Such an instruction can activate another instruction at the same time in the simulation. Accordingly, this only takes place a "delta" later.

8.2 Delay models

The two delay models "Transport-Delay" and "Inertial-Delay" available in VHDL have already been mentioned in the description of the signal assignments.

What both delay models have in common is the so-called "preemptions mechanism", which means that events that have previously been assigned but only become effective after the current signal change have been deleted.

8.2.1 Transport delay model

This delay model, which only becomes effective when it is explicitly identified with the keyword, only uses the "preemptions mechanism" mentioned. With the following signal assignment, which is carried out at time 2 ns, all entries that should take place after time 7 ns are deleted from the event list of the signal:

sig_x <= TRANSPORT '1' AFTER 5 ns;

8.2.2 Inertial deceleration model

The "inertial delay model" is effective by default (without explicit identification). In addition to the "preemption mechanism", it uses the following rule:

  1. Mark a transaction taking place immediately before the new entry that has the same (new) signal value.
  2. Highlight the current and the new transaction.
  3. Delete all unchecked transactions.

This procedure means that only pulses that have a longer (or equal) duration than the specified delay time actually appear on the signal. An assignment of the type:

sig_x <= sig_y AFTER 5 ns;

leads due to the "inertial model" that all pulses of the signal, which have a pulse width of less than 5 ns, do not appear on the signal.